SH7764 Datasheet, PDF (1042/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
(b) Operation when Transmission/Reception is Impossible at Token Issuance Timing
This module cannot issue tokens even at token issuance timing in the following cases. In such a
case, this module attempts transactions at the subsequent interval.
(i) When the PID is set to NAK or STALL.
(ii) When the buffer memory is full at the token sending timing in the receiving (IN) direction.
(iii) When there is no data to be sent in the buffer memory at the token sending timing in the
sending (OUT) direction.
21.4.8 Isochronous Transfers (PIPE1 and PIPE2)
1. This module has the following functions pertaining to isochronous transfers.
2. Notification of isochronous transfer error information
3. Interval counter (specified by the IITV bit)
4. Isochronous IN transfer data setup control (IDLY function)
5. Isochronous IN transfer buffer flush function (specified by the IFIS bit)
This module does not support the High Bandwidth transfers of isochronous transfers.
(1) Error Detection with Isochronous Transfers
This module has a function for detecting the error information noted below, so that when errors
occur in isochronous transfers, software can control them. Tables 21.28 and 21.29 show the
priority in which errors are confirmed and the interrupts that are generated.
(i) PID errors
• If the PID of the packet being received is illegal
(ii) CRC errors and bit stuffing errors
• If an error occurs in the CRC of the packet being received, or the bit stuffing is illegal
(iii) Maximum packet size exceeded
• The maximum packet size exceeded the set value.
(iv) Overrun and underrun errors
• When host controller function is selected:
 When using isochronous IN transfers (reception), the IN token was received but the buffer
memory is not empty.
Rev. 1.00 Nov. 22, 2007 Page 986 of 1692
REJ09B0360-0100