SH7764 Datasheet, PDF (126/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Table 3.12 Floating-Point Control Instructions
Instruction
Operation
Instruction Code
Privileged T Bit
LDS Rm,FPSCR Rm → FPSCR
0100mmmm01101010 —
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LDS Rm,FPUL
Rm → FPUL
0100mmmm01011010 —
—
LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 —
—
LDS.L @Rm+,FPUL (Rm) → FPUL, Rm+4 → Rm 0100mmmm01010110 —
—
STS FPSCR,Rn
FPSCR → Rn
0000nnnn01101010 —
—
STS FPUL,Rn
FPUL → Rn
0000nnnn01011010 —
—
STS.L FPSCR,@-Rn Rn – 4 → Rn, FPSCR → (Rn) 0100nnnn01100010 —
—
STS.L FPUL,@-Rn Rn – 4 → Rn, FPUL → (Rn) 0100nnnn01010010 —
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Table 3.13 Floating-Point Graphics Acceleration Instructions
Instruction
Operation
FMOV DRm,XDn
DRm → XDn
FMOV XDm,DRn
XDm → DRn
FMOV XDm,XDn
XDm → XDn
FMOV @Rm,XDn
(Rm) → XDn
FMOV @Rm+,XDn (Rm) → XDn, Rm + 8 → Rm
FMOV @(R0,Rm),XDn (R0 + Rm) → XDn
FMOV XDm,@Rn
XDm → (Rn)
FMOV XDm,@-Rn Rn – 8 → Rn, XDm → (Rn)
FMOV XDm,@(R0,Rn) XDm → (R0 + Rn)
FIPR FVm,FVn
inner_product (FVm, FVn) →
FR[n+3]
FTRV XMTRX,FVn
transform_vector (XMTRX,
FVn) → FVn
FRCHG
~FPSCR.FR → FPSCR.FR
FSCHG
~FPSCR.SZ → FPSCR.SZ
FPCHG
~FPSCR.PR → FPSCR.PR
FSRRA FRn
1/sqrt(FRn) → FRn
FSCA FPUL,DRn
sin(FPUL) → FRn
cos(FPUL) → FR[n + 1]
Note: * sqrt(FRn) is the square root of FRn.
Instruction Code
1111nnn1mmm01100
1111nnn0mmm11100
1111nnn1mmm11100
1111nnn1mmmm1000
1111nnn1mmmm1001
1111nnn1mmmm0110
1111nnnnmmm11010
1111nnnnmmm11011
1111nnnnmmm10111
1111nnmm11101101
1111nn0111111101
1111101111111101
1111001111111101
1111011111111101
1111nnnn01111101
1111nnn011111101
Privileged T Bit
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Rev. 1.00 Nov. 22, 2007 Page 70 of 1692
REJ09B0360-0100