SH7764 Datasheet, PDF (1301/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.5 Graphic Image Line Offset Registers (GROPSOFST1 to GROPSOFST4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



GROPSOFST[28:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
GROPSOFST[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 29
28 to 0
Initial
Bit Name
Value
R/W

All 0
R
GROPSOFST H'0000000 R/W
[28:0]
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
These bits specify the line offset for the graphic
image. The lower four bits should always be 0000.
GROPSOFST1 to GROPSOFST4
GROPSADR1 to GROPSADR4
Graphic image
area
Memory area for display
Figure 24.10 Graphic Image Memory Area Settings
The start (left side) address of line n is obtained by adding the base address register value
(GROPSADR1 to GROPSADR4) and the line offset (GROPSOFST1 to GROPSOFST4) × n.
Rev. 1.00 Nov. 22, 2007 Page 1245 of 1692
REJ09B0360-0100