SH7764 Datasheet, PDF (1488/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Watchdog Timer and Reset
29.3.4 Watchdog Timer Counter (WDTCNT)
WDTCNT is a 32-bit read-only register that comprises 12-bit watchdog timer counter and counts
up on the WDTBCNT overflow signal. When WDTCNT overflows, a reset is generated in
watchdog timer mode, or an interrupt is generated in interval timer mode. Writing to WDTCNT is
invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

WDTCNT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
29.3.5 Watchdog Timer Base Counter (WDTBCNT)
WDTBCNT is a 32-bit read-only register that comprises 18-bit counter and counts up on the
peripheral clock (Pck). When WDTBCNT overflows, WDTCNT is counted up and WDTBCNT is
cleared to 0. Writing to WDTBCNT is invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
              WDTBCNT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
WDTBCNT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Rev. 1.00 Nov. 22, 2007 Page 1432 of 1692
REJ09B0360-0100