SH7764 Datasheet, PDF (252/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
5. In TLB compatible mode, execute the LDTLB instruction and write the contents of PTEH and
PTEL to the TLB.
In TLB extended mode, execute the LDTLB instruction and write the contents of PTEH,
PTEL, PTEA to the UTLB.
6. Finally, execute the exception handling return instruction (RTE), terminate the exception
handling routine, and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
Rev. 1.00 Nov. 22, 2007 Page 196 of 1692
REJ09B0360-0100