SH7764 Datasheet, PDF (531/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Timer Unit (TMU)
14.3.2 Timer Start Register (TSTR0, TSTR1)
TSTR is an 8-bit readable/writable register that specifies whether TCNT in each channel is
operated or stopped.
• TSTR0
BIt: 7
6
5
4
3
2
1
0
— — — — — STR2 STR1 STR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W
Bit
7 to 3
2
1
0
Bit Name
—
STR2
STR1
STR0
Initial
Value R/W
All 0 R
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Counter Start 2
Specifies whether TCNT2 is operated or stopped.
0: TCNT2 count operation is stopped
1: TCNT2 performs count operation
Counter Start 1
Specifies whether TCNT1 is operated or stopped.
0: TCNT1 count operation is stopped
1: TCNT1 performs count operation
Counter Start 0
Specifies whether TCNT0 is operated or stopped.
0: TCNT0 count operation is stopped
1: TCNT0 performs count operation
Rev. 1.00 Nov. 22, 2007 Page 475 of 1692
REJ09B0360-0100