SH7764 Datasheet, PDF (982/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Table 21.15 Information Cleared by this Module by Setting ACLRM = 1
Information Cleared by ACLRM Bit
No. Manipulation
Cases in which Clearing the Information
is Necessary
1 All the information in the FIFO buffer
assigned to the pertinent pipe
2 When the host controller function is selected, When the interval count value is to be reset
the interval count value when the pertinent
pipe is for isochronous transfer
3 Values of the internal flags related to the
BFRE bit
When the BFRE setting is modified
4 Values of the internal flags related to the
transaction count
When the transaction count function is
forcibly terminated
21.3.37 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)
PIPEnTRE is a register that enables or disables the transaction counter corresponding to PIPE1 to
PIPE5, and clears the transaction counter.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
— TRENB TRCLR —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R
R
R
R
R
R
R
R
Bit
Bit Name
15 to 10 
Initial
Value R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 926 of 1692
REJ09B0360-0100