SH7764 Datasheet, PDF (729/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
26
OIRQ
0
R/W* Overflow Error Interrupt Status Flag
This status flag indicates that the data has been
supplied at a higher rate than the required rate.
This bit is set to 1 regardless of the setting of OIEN bit.
In order to clear it to 0, write 0 to it.
If OIRQ = 1 and OIEN = 1, then an interrupt will be
generated.
• TRMD = 0 (Receive mode)
If OIRQ = 1, it indicates that the previous unread
data had not been read out before new unread data
was written in SSIRDR0 to SSIRDR5. This may
cause the loss of data, which may cause destruction
of multi-channel data.
Note: If an overflow error occurs, the data in the
data buffer will be overwritten by the next
data sent from the SSI interface.
• TRMD = 1 (Transmit mode)
If OIRQ = 1, it indicates that SSITDR0 to SSITDR5
had data written in before the data in SSITDR0 to
SSITDR5 were transferred to the shift register. This
may cause the loss of data, which can lead to
destruction of multi-channel data.
25
IIRQ
1
R
Idle Mode Interrupt Status Flag
This status flag indicates whether the SSI_CH0 to
SSI_CH5 are in the idle status. This bit is set to 1
regardless of the setting of IIEN bit, so that polling will
be possible.
The interrupt can be masked by clearing IIEN bit to 0,
but writing 0 in this bit will not clear the interrupt.
If IIRQ = 1 and IIEN = 1, then an interrupt will be
generated.
0: The SSI_CH0 to SSI_CH5 are not in the idle status.
1: The SSI_CH0 to SSI_CH5 are in the idle status.
Rev. 1.00 Nov. 22, 2007 Page 673 of 1692
REJ09B0360-0100