SH7764 Datasheet, PDF (211/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues
(SQs). In user mode, the access right is specified by the SQMD bit in MMUCR. For details, see
section 8.7, Store Queues.
The area from H'E500 0000 to H'E5FF FFFF comprises addresses for accessing the on-chip
memory. In user mode, the access right is specified by the RMD bit in RAMCR. For details, see
section 9, On-Chip Memory.
The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache
address array. For details, see section 8.6.1, IC Address Array.
The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data
array. For details, see section 8.6.2, IC Data Array.
The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB
address array. For details, see section 7.7.1, ITLB Address Array.
The area from H'F300 0000 to H'F37F FFFF is used for direct access to instruction TLB data
array. For details, see section 7.7.2, ITLB Data Array (TLB Compatible Mode) and section 7.7.3,
ITLB Data Array (TLB Extended Mode).
The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address
array. For details, see section 8.6.3, OC Address Array.
The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data
array. For details, see section 8.6.4, OC Data Array.
The area from H'F600 0000 to H'F60F FFFF is used for direct access to the unified TLB address
array. For details, see section 7.7.4, UTLB Address Array.
The area from H'F700 0000 to H'F70F FFFF is used for direct access to unified TLB data array.
For details, see section 7.7.5, UTLB Data Array (TLB Compatible Mode) and section 7.7.6,
UTLB Data Array (TLB Extended Mode).
The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register
area. For details, see register descriptions in each section.
(2) Physical Address Space
The SH-4A supports a 29-bit physical address space. The physical address space is divided into
eight areas as shown in figure 7.5. Area 7 is a reserved area. For details, see section 11, Memory
Controller Unit (MCU).
Rev. 1.00 Nov. 22, 2007 Page 155 of 1692
REJ09B0360-0100