SH7263 Datasheet, PDF (998/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
Bit[15:0]: MBIMR1 Description
0
Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled
1
Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)
• MBIMR0
Bit: 15
Initial value: 1
R/W: R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
7
6
MBIMR0[15:0]
1
1
1
R/W R/W R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Bit 15 to 0 — Enable or disable interrupt requests from individual Mailbox-15 to Mailbox-0
respectively.
Bit[15:0]: MBIMR0 Description
0
Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled
1
Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)
(8) Unread Message Status Register (UMSR)
This register is a 32-bit read/conditionally write register and it records the mailboxes whose
contents have not been accessed by the CPU prior to a new message being received. If the CPU
has not cleared the corresponding bit in the RXPR or RFPR when a new message for that mailbox
is received, the corresponding UMSR bit is set to ‘1’. This bit may be cleared by writing a ‘1’ to
the corresponding bit location in the UMSR. Writing a ‘0’ has no effect.
If a mailbox is configured as transmit box, the corresponding UMSR will not be set.
• UMSR1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UMSR1[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only when writing a ‘1’ to clear.
Rev. 2.00 Mar. 14, 2008 Page 964 of 1824
REJ09B0290-0200