SH7263 Datasheet, PDF (78/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.1.3 System Registers
The system registers consist of four 32-bit registers: the high and low multiply and accumulate
registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH
and MACL store the results of multiply or multiply and accumulate operations. PR stores the
return address from a subroutine procedure. PC indicates the address four bytes ahead of the
instruction being executed and controls the flow of the processing.
31
MACH
MACL
0 _{Multiply and accumulate register high (MACH) and multiply}
and accumulate register low (MACL):
Store the results of multiply or multiply and accumulate operations.
31
PR
0 _{Procedure register (PR):}
Stores the return address from a subroutine procedure.
31
PC
0 _{Program counter (PC):}
Indicates the four bytes ahead of the current instruction.
Figure 2.3 System Registers
(1) Multiply and Accumulate Register High (MACH) and Multiply and Accumulate
Register Low (MACL)
MACH and MACL are used as the addition value in a MAC instruction, and store the result of a
MAC or MUL instruction.
(2) Procedure Register (PR)
PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is
referenced by a subroutine return instruction (RTS).
(3) Program Counter (PC)
PC indicates the address four bytes ahead of the instruction being executed.
Rev. 2.00 Mar. 14, 2008 Page 44 of 1824
REJ09B0290-0200