SH7263 Datasheet, PDF (1027/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
<Potential> Time Master
<Configuration> Cycle Time varies between L and Time_Ref + L
Cycle Time = 0
=L
= Time_Ref + L
Time_Mark 1 Time_Mark 2 Time_Mark 3 Time_Mark 4 Time_Mark 5 Time_Mark 6 Time_Ref
TTT in MB24 TTT in MB25 TTT in MB26 TTT in MB27 TTT in MB28 TTT in MB29 TTT in MB30
Watch_Trigger
TCMR2
copy CCR from received time reference at reception completion
(no reception in Time Master)
increment CCR
(updated CCR has to be transmitted)
<Normal Operation>
capture timestamp
at SOF of transmission
CCR = 0
Time_Mark 1 Time_Mark 2 Time_Mark 3 Time_Mark 4 Time_Mark 5 Time_Mark 6 Time_Ref
TTT in MB24 TTT in MB25 TTT in MB26 TTT in MB27 TTT in MB28 TTT in MB29 TTT in MB30
CCR = 1
Ref_Mark is updated
at successful end of time reference transmission
CCR = 1
CCR = 1
L
Time_Mark 1 Time_Mark 2 Time_Mark 3 Time_Mark 4 Time_Mark 5 Time_Mark 6 Time_Ref
TTT in MB24 TTT in MB25 TTT in MB26 TTT in MB27 TTT in MB28 TTT in MB29 TTT in MB30
Cycle Time
= Time_Ref
= Time_Ref + L
CCR = 2
Figure 19.19 (Potential) Time Master
Rev. 2.00 Mar. 14, 2008 Page 993 of 1824
REJ09B0290-0200