SH7263 Datasheet, PDF(108/1862 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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SH7263 Datasheet, PDF (108/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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Section 2 CPU

2.4.4 Logic Operation Instructions

Table 2.13 Logic Operation Instructions

Instruction

Instruction Code

Operation

Execu-

tion

Cycles

Compatibility

SH2,

T Bit SH2E SH4 SH-2A

AND

Rm,Rn

0010nnnnmmmm1001 Rn & Rm â Rn

1

â¯ Yes Yes Yes

AND

#imm,R0

11001001iiiiiiii R0 & imm â R0

1

â¯ Yes Yes Yes

AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm â

3

(R0 + GBR)

â¯ Yes Yes Yes

NOT

Rm,Rn

0110nnnnmmmm0111 ~Rm â Rn

1

â¯ Yes Yes Yes

OR

Rm,Rn

0010nnnnmmmm1011 Rn | Rm â Rn

1

â¯ Yes Yes Yes

OR

#imm,R0

11001011iiiiiiii R0 | imm â R0

1

â¯ Yes Yes Yes

OR.B

#imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm â

3

(R0 + GBR)

â¯ Yes Yes Yes

TAS.B @Rn

0100nnnn00011011 When (Rn) is 0, 1 â T

3

Otherwise, 0 â T,

1 â MSB of(Rn)

Test Yes Yes Yes

result

TST

Rm,Rn

0010nnnnmmmm1000

Rn & Rm

1

When the result is 0, 1 â T

Otherwise, 0 â T

Test Yes Yes Yes

result

TST

#imm,R0

11001000iiiiiiii

R0 & imm

1

When the result is 0, 1 â T

Otherwise, 0 â T

Test Yes Yes Yes

result

TST.B

#imm,@(R0,GBR)

11001100iiiiiiii

(R0 + GBR) & imm

3

When the result is 0, 1 â T

Otherwise, 0 â T

Test Yes Yes Yes

result

XOR

Rm,Rn

0010nnnnmmmm1010 Rn ^ Rm â Rn

1

â¯ Yes Yes Yes

XOR

#imm,R0

11001010iiiiiiii R0 ^ imm â R0

1

â¯ Yes Yes Yes

XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm â

3

(R0 + GBR)

â¯ Yes Yes Yes

Rev. 2.00 Mar. 14, 2008 Page 74 of 1824

REJ09B0290-0200

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