SH7263 Datasheet, PDF (470/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.17 shows the TEND output timing.
CKIO
Bus cycle
DREQ
DACK
DMAC
End of DMA transfer
CPU
DMAC
CPU
CPU
TEND
Figure 10.17 Example of DMA Transfer End Signal Timing
(Cycle Steal Mode Level Detection)
The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is
performed for an 8-bit, 16-bit, or 32-bit external device, when longword access is performed for
an 8-bit or 16-bit external device, or when word access is performed for an 8-bit external device.
When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the
CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS
signal for data alignment as shown in figure 10.18. Figures 10.13 to 10.17 show the cases where
DACK and TEND are not divided in the DMA transfer.
Rev. 2.00 Mar. 14, 2008 Page 436 of 1824
REJ09B0290-0200