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| SH7263 Datasheet, PDF (1106/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series | |||
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Section 20 IEBusTM Controller (IEB)
20.6.2 Slave Receive Operation
Figure 20.14 shows the timing for slave receive operation.
IEFLG
RSS
CMX
MRQ
SRQ
SRE
Broadcast
reception
DL
Dn-1 Dn
Slave
reception
HD MA SA CT DL D1 D2
IERSR
RXS
RXF
[Legend]
HD: Header
MA: Master address field
SA: Slave address field
CT: Control field
DL: Message length field
Dn: Data field
Figure 20.14 Slave Receive Operation Timing
Dn-1 Dn
Rev. 2.00 Mar. 14, 2008 Page 1072 of 1824
REJ09B0290-0200
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