SH7263 Datasheet, PDF (1735/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
Bφ = 66.66 MHz*¹*²
Item
Symbol Min.
Max.
Unit Figure
RAS delay time 1
RAS delay time 2
CAS delay time 1
CAS delay time 2
DQM delay time 1
t
RASD1
t_RASD2
t_CASD1
t
CASD2
t_DQMD1
1
1/2t_cyc
1
1/2t
cyc
1
13
ns
1/2t_cyc + 13 ns
13
ns
1/2t + 13 ns
cyc
13
ns
Figures 35.22 to
35.38
Figures 35.39, 35.40
Figures 35.22 to
35.38
Figures 35.39, 35.40
Figures 35.22 to
35.35
DQM delay time 2
CKE delay time 1
CKE delay time 2
AH delay time
Multiplexed address delay
time
t_DQMD2
t
CKED1
t
CKED2
t
AHD
t
MAD
1/2t_cyc
1
1/2t
cyc
1/2t
cyc
—
1/2t_cyc + 13 ns
13
ns
1/2t + 13 ns
cyc
1/2t + 13 ns
cyc
13
ns
Figures 35.39, 35.40
Figure 35.37
Figure 35.40
Figure 35.17
Figure 35.17
Multiplexed address hold time t_MAH
Address setup time relative to t_AWH
AH
1
—
1/2t_cyc - 2 —
ns
Figure 35.17
ns
Figure 35.17
DACK, TEND delay time
t_DACD
Refer to DMAC timing ns
Figures 35.13 to
35.35, 35.39, 35.41
to 35.44
FRAME delay time
t
0
13
ns
Figure 35.18
FMD
ICIORD delay time
t
—
ICRSD
1/2t + 13 ns
cyc
Figures 35.43, 35.44
ICIOWR delay time
t_ICWSD
—
1/2t_cyc + 13 ns
Figures 35.43, 35.44
Notes: 1. The maximum value (fmax) of Bφ (external bus clock) depends on the number of wait
cycles and the system configuration of your board.
2. 1/2 t indicated in minimum and maximum values for the item of delay, setup, and hold
cyc
times represents a half cycle from the rising edge with a clock. That is, 1/2 t describes
cyc
a reference of the falling edge with a clock.
Rev. 2.00 Mar. 14, 2008 Page 1701 of 1824
REJ09B0290-0200