SH7263 Datasheet, PDF (82/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.3 Instruction Features
2.3.1 RISC-Type Instruction Set
Instructions are RISC type. This section details their functions.
(1) 16-Bit Fixed-Length Instructions
Basic instructions have a fixed length of 16 bits, improving program code efficiency.
(2) 32-Bit Fixed-Length Instructions
The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease
of use.
(3) One Instruction per State
Each basic instruction can be executed in one cycle using the pipeline system.
(4) Data Length
Longword is the standard data length for all operations. Memory can be accessed in bytes, words,
or longwords. Byte or word data in memory is sign-extended and handled as longword data.
Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It
is also handled as longword data.
Table 2.2 Sign Extension of Word Data
SH2-A CPU
Description
MOV.W
ADD
.DATA.W
@(disp,PC),R1 Data is sign-extended to 32
R1,R0
bits, and R1 becomes
H'00001234. It is next
.........
operated upon by an ADD
H'1234
instruction.
Note: @(disp, PC) accesses the immediate data.
Example of Other CPU
ADD.W #H'1234,R0
(5) Load-Store Architecture
Basic operations are executed between registers. For operations that involve memory access, data
is loaded to the registers and executed (load-store architecture). Instructions such as AND that
manipulate bits, however, are executed directly in memory.
Rev. 2.00 Mar. 14, 2008 Page 48 of 1824
REJ09B0290-0200