SH7263 Datasheet, PDF (1357/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Register
Name
DCPCFG
PIPECFG
Bit Name
EPNUM
SHTNAK
PIPEBUF BUFSIZE
BUFNMB
DCPMAXP MXPS
PIPEMAXP
PIPEPERI IFIS
IITV
DCPCTR BSTS
PIPExCTR INBUFM
ACLRM
SQCLR
SQSET
SQMON
PID
Setting
Contents
Remarks
Endpoint number See section 25.4.3 (2), Endpoint Number
Selects disabled
state for pipe
when transfer
ends
PIPE1 and PIPE2: Can be set (only when bulk
transfer has been selected)
PIPE3 to PIPE5: Can be set
Buffer memory
size
DCP: Cannot be set (fixed at 256 bytes)
PIPE1 to PIPE5: Can be set (a maximum of 2 kbytes
in 64-byte units can be specified)
PIPE6 and PIPE7: Cannot be set (fixed at 64 bytes)
Buffer memory
number
DCP: Cannot be set (areas fixed at H'0 to H'3)
PIPE1 to PIPE5: Can be set (can be specified in
areas H'6 to H'7F)
PIPE6 to PIPE7: Cannot be set (areas fixed at H'4
and H'5)
Maximum packet See section 25.4.3 (3), Maximum Packet Size Setting
size
Buffer flush
PIPE1 and PIPE2: Can be set (only when
isochronous transfer has been
selected)
PIPE3 to PIPE7: Cannot be set
Interval counter PIPE1 and PIPE2: Can be set (only when
isochronous transfer has been
selected)
PIPE3 to PIPE7: Cannot be set
Buffer status Also related to the DIR/ISEL bit
IN buffer monitor Also related to the DIR/ISEL bit
Auto buffer clear Enabled/disabled setting can be set when the buffer
memory reading is set.
Sequence clear Clears the data toggle bit
Sequence set Sets the data toggle bit
Sequence
confirm
Confirms the data toggle bit
Response PID See section 25.4.3 (4), Response PID
Rev. 2.00 Mar. 14, 2008 Page 1323 of 1824
REJ09B0290-0200