SH7263 Datasheet, PDF (760/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
4
RE
0
R/W Receive Enable
Enables or disables the serial receiver.
0: Receiver disabled*¹
1: Receiver enabled*²
Notes:1. Clearing RE to 0 does not affect the receive
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
2. Serial reception starts when a start bit is
detected in asynchronous mode, or
synchronous clock is detected in clock
synchronous mode. Select the receive format
in SCSMR and SCFCR and reset the receive
FIFO before setting RE to 1.
3
REIE
0
R/W Receive Error Interrupt Enable
Enables or disables the receive-error (ERI) interrupts
and break (BRI) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERI) and break interrupt
(BRI) requests are disabled
1: Receive-error interrupt (ERI) and break interrupt
(BRI) requests are enabled*
Note: * ERI or BRI interrupt requests can be
cleared by reading the ER, BR or ORER
flag after it has been set to 1, then clearing
the flag to 0, or by clearing RIE and REIE to
0. Even if RIE is set to 0, when REIE is set
to 1, ERI or BRI interrupt requests are
enabled. Set so If SCIF wants to inform
INTC of ERI or BRI interrupt requests
during DMA transfer.
Rev. 2.00 Mar. 14, 2008 Page 726 of 1824
REJ09B0290-0200