SH7263 Datasheet, PDF (1844/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
35.4.2 Control Signal
Timing
Table 35.7 Control
Signal Timing
Page
1698
Revision (See Manual for Details)
Table amended
Bφ = 66.66 MHz
Item
Symbol
Bus buffer off time 1
t_BOFF1
Bus buffer off time 2
t_BOFF2
Bus buffer on time 1
t_BON1
Bus buffer on time 2
t_BON2
BACK setup time when bus buffer off t
BACKS
Min.
—
—
—
—
0
Max.
15
15
15
15
—
Unit
ns
ns
ns
ns
ns
Figure 35.12 Bus
Release Timing
1700 Figure amended
BACK
A25 to A0,
D31 to D0
t_BACKD
t_BACKS
t_BOFF1
t_BOFF2
t_BACKD
t_BON1
t_BON2
35.4.3 Bus Timing
Table 35.8 Bus Timing
1701 to
1703
Table and notes amended
Item
Address delay time 1
Symbol
t
AD1
Bφ = 66.66 MHz*¹*²
Min.
Max.
1
13
Unit
ns
Chip enable setup time
t_CS
0
—
ns
CS delay time 1
t_CSD1
1
13
ns
Read write delay time 1
t
1
13
ns
RWD1
WAIT setup time
t_WTS
WAIT hold time
t_WTH
Address setup time relative to t
AWH
AH
DACK, TEND delay time
t_DACD
1/2t_cyc + 5.5 —
ns
1/2t_cyc + 4.5 —
ns
1/2t - 2 —
ns
cyc
Refer to DMAC timing ns
Figure
Figures 35.13 to
35.38, 35.40 to
35.44
Figures 35.13 to
35.16, 35.21
Figures 35.13 to
35.38, 35.41 to
35.44
Figures 35.13 to
35.38, 35.41 to
35.44
Figures 35.14 to
35.21, 35.42, 35.44
Figures 35.14 to
35.21, 35.42, 35.44
Figure 35.17
Figures 35.13 to
35.35, 35.39, 35.41
to 35.44
Notes: 1. The maximum value (fmax) of Bφ (external bus
clock) depends on the number of wait cycles and
the system configuration of your board.
2. 1/2 t indicated in minimum and maximum values
cyc
for the item of delay, setup, and hold times
represents a half cycle from the rising edge with a
clock. That is, 1/2 t_cyc describes a reference of the
falling edge with a clock.
Rev. 2.00 Mar. 14, 2008 Page 1810 of 1824
REJ09B0290-0200