SH7263 Datasheet, PDF (798/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Figure 15.5 shows an example of the operation for transmission.
Serial
data
Start
1 bit
0 D0
Data
Parity Stop Start
bit bit bit
D1
D7 0/1 1
0 D0
Data
Parity Stop
bit
bit
1
D1
D7 0/1 1
Idle state
(mark state)
TDFE
TEND
TXI interrupt
request
Data written to SCFTDR and TDFE
flag read as 1 then cleared to 0 by
TXI interrupt handler
One frame
TXI interrupt
request
Figure 15.5 Example of Transmit Operation
(8-Bit Data, Parity, 1 Stop Bit)
4. When modem control is enabled in channel 3, transmission can be stopped and restarted in
accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the
line goes to the mark state after transmission of one frame. When CTS is set to 0, the next
transmit data is output starting from the start bit.
Figure 15.6 shows an example of the operation when modem control is used.
Serial data
TxD
Start
bit
0 D0 D1
Parity Stop
bit bit
D7 0/1
Start
bit
0 D0 D1
D7 0/1
CTS
Drive high before stop bit
Figure 15.6 Example of Operation Using Modem Control (CTS)
Rev. 2.00 Mar. 14, 2008 Page 764 of 1824
REJ09B0290-0200