SH7263 Datasheet, PDF (190/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.4 Interrupt Sources
There are six types of interrupt sources: NMI, user break, H-UDI, IRQ, PINT, and on-chip
peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the
highest. When set to level 0, that interrupt is masked at all times.
6.4.1 NMI Interrupt
The NMI interrupt has a priority level of 16 and is accepted at all times. NMI interrupt requests
are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0)
selects whether the rising edge or falling edge is detected.
Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the
interrupt mask level bits (I3 to I0) in the status register (SR) to level 15.
6.4.2 User Break Interrupt
A user break interrupt which occurs when a break condition set in the user break controller (UBC)
matches has a priority level of 15. The user break interrupt exception handling sets the I3 to I0 bits
in SR to level 15. For user break interrupts, see section 7, User Break Controller (UBC).
6.4.3 H-UDI Interrupt
The user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs at serial
input of an H-UDI interrupt instruction. H-UDI interrupt requests are edge-detected and retained
until they are accepted. The H-UDI interrupt exception handling sets the I3 to I0 bits in SR to level
15. For H-UDI interrupts, see section 33, User Debugging Interface (H-UDI).
6.4.4 IRQ Interrupts
IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge,
rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense
select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The
priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority
registers 01 and 02 (IPR01 and IPR02).
When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the INTC
while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the
INTC when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be
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