SH7263 Datasheet, PDF (1833/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page Revision (See Manual for Details)
25.3.7 FIFO Port Select 1249
Registers (CFIFOSEL,
D0FIFOSEL,
D1FIFOSEL)
(1) CFIFOSEL
Bit table amended
Bit: 15 14
RCNT REW
Initial value: 0
0
R/W: R/W R/W*¹
1249 to
1250
Table amended
Initial
Bit
Bit Name
Value
14
REW
0
11, 10 MBW[1:0]
00
5
ISEL
0
2 to 0 CURPIPE[2:0] 000
R/W Description
R/W*¹ Buffer Pointer Rewind
0: Invalid
1: The buffer pointer is rewound.
R/W FIFO Port Access Bit Width
00: 8-bit width
01: 16-bit width
10: 32-bit width
11: Setting prohibited
When the selected CURPIPE is set to the buffer
memory read direction, use either of the following
methods to set these bits:
• Write to the MBW bits and set the CURPIPE bits
simultaneously.
• When the DCP (CURPIPE = 000) setting is
selected, write to the MBW bits and set the ISEL
bit simultaneously.
For details, see 25.4.4, Buffer Memory.
Note: Once reading from the buffer memory is
started, the access bit width of the FIFO port
cannot be changed until all of the data has
been read. Also, the bit width cannot be
changed from the 8-bit width to the 16-/32-bit
width or from the 16-bit width to the 32-bit width
while data is being written to the buffer
memory.
R/W FIFO Port Access Direction When DCP is Selected*²
0: Reading from the buffer memory is selected
1: Writing to the buffer memory is selected
This bit is valid only when DCP is selected with the
CURPIPE bit.
This bit should be set according to either of the
following procedures:
• Set the CURPIPE bits to DCP (CURPIPE = 000)
and set this bit at the same time.
• Set the CURPIPE bits to DCP (CURPIPE = 000),
wait for 200 ns, and then set this bit.
For details, see section 25.4.4, Buffer Memory.
R/W FIFO Port Access Pipe Specification*²
000: DCP
100: Pipe 4
001: Pipe 1
101: Pipe 5
010: Pipe 2
110: Pipe 6
011: Pipe 3
111: Pipe 7
Rev. 2.00 Mar. 14, 2008 Page 1799 of 1824
REJ09B0290-0200