SH7263 Datasheet, PDF (1059/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Table 20.5 Control Field for Locked Slave Unit
Setting Value
H'0
H'4
H'5
Bit 3
0
0
0
Bit 2
0
1
1
Bit 1
0
0
0
Bit 0
0
0
1
Section 20 IEBus^TM Controller (IEB)
Function
Reads slave status
Reads locked address (upper 8 bits)
Reads locked address (lower 4 bits)
(1) Slave Status Read (Control Bits: H'0, H'6)
The master unit can decide the reason the slave unit does not return the acknowledgement (ACK)
by reading the slave status (H'0, H'6). The slave status indicates the result of the last
communications that the slave unit performed. All slave units can provide slave status
information. Figure 20.2 shows the bit configuration of the slave status.
MSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB
Bit 0
Bit
Bit 7, bit 6
Bit 5
Bit 4*²
Bit 3
Bit 2
Bit 1*³
Bit 0*⁴
Value
00
01
10
11
0
0
1
0
0
1
0
1
0
1
Description
Mode 0
Mode 1
Mode 2
Indicates the highest mode
supported by a unit. *¹
For future use
Fixed 0
Slave transmission halted
Slave transmission enabled
Fixed 0
Unit is unlocked
Unit is locked
Slave receive buffer is empty
Slave receive buffer is not empty
Slave transmit buffer is empty
Slave transmit buffer is not empty
Notes:
1. Since this LSI can support up to mode 2, bits 6 and 7 are fixed to 10.
2. The value of bit 4 can be selected by the STE bit in the IEBus master unit address register 1 (IEAR1).
3. The slave receive buffer is a buffer which is accessed during data write
(control bits: H'A, H'B, H'E, H'F).
In this LSI, the slave receive buffer corresponds to the IEBus receive buffer register (IERB001 to IERB128);
and bit 2 is the value of the RXBSY bit in the IEBus receive status register (IERSR).
4. The slave transmit buffer is a buffer which is accessed during data read
(control bits: H'3, H'7).
In this LSI, the slave transmit buffer corresponds to the IEBus transmit buffer register
(IETB001 to IETB128) and bit 0 is the value of the SRQ bit in the IEBus general flag registers (IEFLG).
Figure 20.2 Bit Configuration of Slave Status (SSR)
Rev. 2.00 Mar. 14, 2008 Page 1025 of 1824
REJ09B0290-0200