SH7263 Datasheet, PDF (110/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.4.6 Branch Instructions
Table 2.15 Branch Instructions
Instruction
BF
label
BF/S
label
BT
label
BT/S
label
BRA
label
BRAF Rm
BSR
label
BSRF Rm
JMP
JSR
@Rm
@Rm
Instruction Code
Operation
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
10001011dddddddd
When T = 0, disp × 2 + PC → 3/1*
PC,
When T = 1, nop
⎯ Yes Yes Yes
10001111dddddddd
Delayed branch
2/1*
When T = 0, disp × 2 + PC →
PC,
When T = 1, nop
⎯ Yes Yes Yes
10001001dddddddd
When T = 1, disp × 2 + PC → 3/1*
PC,
When T = 0, nop
⎯ Yes Yes Yes
10001101dddddddd
Delayed branch
2/1*
When T = 1, disp × 2 + PC →
PC,
When T = 0, nop
⎯ Yes Yes Yes
1010dddddddddddd Delayed branch,
disp × 2 + PC → PC
2
⎯ Yes Yes Yes
0000mmmm00100011 Delayed branch,
Rm + PC → PC
2
⎯ Yes Yes Yes
1011dddddddddddd Delayed branch, PC → PR, 2
disp × 2 + PC → PC
⎯ Yes Yes Yes
0000mmmm00000011 Delayed branch, PC → PR, 2
Rm + PC → PC
⎯ Yes Yes Yes
0100mmmm00101011 Delayed branch, Rm → PC 2
⎯ Yes Yes Yes
0100mmmm00001011 Delayed branch, PC → PR, 2
Rm → PC
⎯ Yes Yes Yes
JSR/N @Rm
0100mmmm01001011 PC-2 → PR, Rm → PC
3
JSR/N @@(disp8,TBR) 10000011dddddddd PC-2 → PR,
5
(disp × 4 + TBR) → PC
RTS
0000000000001011 Delayed branch, PR → PC 2
RTS/N
0000000001101011 PR → PC
3
RTV/N Rm
0000mmmm01111011 Rm → R0, PR → PC
3
Note: * One cycle when the program does not branch.
Rev. 2.00 Mar. 14, 2008 Page 76 of 1824
REJ09B0290-0200
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Yes
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Yes
⎯ Yes Yes Yes
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Yes
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Yes