SH7263 Datasheet, PDF (1303/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
2 to 0 CTSQ[2:0] 000
R
Control Transfer Stage
000: Idle or setup stage
001: Control read data stage
010: Control read status stage
011: Control write data stage
100: Control write status stage
101: Control write (no data) status stage
110: Control transfer sequence error
111: Setting prohibited
Notes: 1. Only 0 can be written to.
2. If multiple sources have occurred among the VBINT, RESM, SOFR, DVST, and CTRT
bits, an access cycle of at least 140 ns and 3 bus clock cycles is required in order to
clear the bits in succession, not simultaneously.
3. This bit is initialized to 1 when the VBUS pin is high level and 0 when it is low level.
4. These bits are initialized to B'000 by a power-on reset or a software reset, and B'001 by
a USB bus reset.
25.3.17 Interrupt Status Register 1 (INTSTS1)
INTSTS1 is a register that is used to confirm interrupt status. The SOFR, BEMP, NRDY and
BRDY bits are mirror bits of INTSTS0. When these bits are read, the corresponding bit values in
INTSTS0 will be read. When these bits in INTSTS1 are written to, the written values are also
reflected in INTSTS0.
Interrupt generation can be confirmed simply by referencing one of the registers: INTSTS0 when
the peripheral controller function is selected and INTSTS1 when the host controller function is
selected.
This register is initialized by a power-on reset or a software reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
- BCHG SOFR DTCH - BEMP NRDY BRDY -
- SIGN SACK -
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W* R/W* R/W* R
R
R
R
R
R R/W* R/W* R
R
R
R
Rev. 2.00 Mar. 14, 2008 Page 1269 of 1824
REJ09B0290-0200