SH7263 Datasheet, PDF (1045/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
Section 20 IEBus^TM Controller (IEB)
This LSI has an on-chip one-channel IEBus controller (IEB). The Inter Equipment Bus^TM
(IEBus^TM)* is a small-scale digital data transfer system for inter-equipment data transfer.
This LSI does not have an on-chip IEBus driver/receiver, so it is necessary to mount a dedicated
driver/receiver externally. In addition, as the IERxD and IETxD pins need 3V to operate, a
dedicated external level shifter is necessary.
Note: * The Inter Equipment Bus^TM (IEBus^TM) is a trademark of NEC Electronics Corporation.
20.1 Features
• IEBus protocol control (layer 2) supported
⎯ Half-duplex asynchronous communications
⎯ Multi-master system
⎯ Broadcast communications function
⎯ Selectable mode (three types) with different transfer speeds
• On-chip buffers for data transmission and reception
⎯ Transmission and reception buffers: 128 bytes each
⎯ Up to 128 bytes of consecutive transmit/reception (maximum number of transfer bytes in
mode 2)
• Operating frequency
⎯ 12 MHz, 12.58 MHz (IEB uses 1/2 divided clocks of Pφ, or AUDIO_X1*, AUDIO_X2*.)
⎯ 18 MHz, 18.87 MHz (IEB uses 1/3 divided clocks of Pφ, or AUDIO_X1*, AUDIO_X2*.)
⎯ 24 MHz, 25.16 MHz (IEB uses 1/4 divided clocks of Pφ, or AUDIO_X1*, AUDIO_X2*.)
⎯ 30 MHz, 31.45 MHz (IEB uses 1/5 divided clocks of Pφ, or AUDIO_X1*, AUDIO_X2*.)
⎯ 36 MHz, 37.74 MHz (IEB uses 1/6 divided clocks of AUDIO_X1* or AUDIO_X2*.)
Note: * Available as the IEB clock input only when not used as the clock input for SSI audio
• Module standby mode can be set.
Rev. 2.00 Mar. 14, 2008 Page 1011 of 1824
REJ09B0290-0200