SH7263 Datasheet, PDF (1782/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
35.4.14 FLCTL Timing
Table 35.19 AND Type Flash Memory Interface Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0V, Ta = −40 to 85 °C
Item
Command issue setup time
Command issue hold time
Data output setup time
Data output hold time
Data output setup time 2
Data output hold time 2
FWE cycle time
FWE low pulse width
Symbol Min.
tACDS
2 × tfcyc − 10
tACDH
2 × tfcyc − 10
tADOS
tfcyc − 10
tADOH
tfcyc − 10
tADOS2
0.5 × tfcyc − 10
tADOH2
0.5 × tfcyc − 10
tACWC
2 × tfcyc − 5
tAWP
tfcyc − 5
FWE high pulse width
tAWPH
Command to address transition time tACAS
Address to data read transition time tAADDR
Address to ready/busy transition time tAADRB
Ready/busy to data read transition
time
tARBDR
Data read setup time
tADRS
FSC cycle time
tASCC
FSC high pulse width
tASP
FSC low pulse width
tASPL
Read data setup time
tARDS
Read data hold time
tARDH
Status read data setup time
tASRDS
Address to data write transition time tAADDW
tfcyc − 5
4 × tfcyc
32 × tpcyc
⎯
3 × tfcyc
tfcyc − 10
tfcyc − 5
0.5 × tfcyc − 5
0.5 × tfcyc − 5
24
5
2 × tfcyc + 24
4 × tpcyc
Max. Unit Figure
⎯
ns Figures 35.64,
⎯
ns ^35.68
⎯
ns Figures 35.64,
⎯
ns ^{35.65, 35.68}
⎯
ns Figure 35.67
⎯
ns
⎯
ns Figure 35.65
⎯
ns Figures 35.64,
35.65, 35.68
⎯
ns Figure 35.65
⎯
ns
⎯
ns Figure 35.66
35 × tpcyc ns
⎯
ns
⎯
ns Figure 35.66
⎯
ns Figures 35.66,
⎯
ns ^35.67
⎯
ns
⎯
ns Figures 35.66,
⎯
ns ^35.68
⎯
ns Figure 35.68
⎯
ns Figure 35.67
Rev. 2.00 Mar. 14, 2008 Page 1748 of 1824
REJ09B0290-0200