SH7263 Datasheet, PDF (283/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
5 to 2 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
HW[1:0]
00
R/W Delay Cycles from RD, WEn Negation to Address, CS0
Negation
Specify the number of delay cycles from RD and WEn
negation to address and CS0 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Note: * To connect the burst ROM to the CS0 space and switch to burst ROM interface after
activation, set the TYPE[2:0] bits in CS0BCR after setting the burst number by the bits
20 and 21 and the burst wait cycle number by the bits16 and 17. Do not write 1 to the
reserved bits other than above bits.
• CS1WCR, CS7WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
BAS
-
WW[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Bit
Bit Name
31 to 21 ⎯
Initial
Value
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 249 of 1824
REJ09B0290-0200