SH7263 Datasheet, PDF (1146/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.26 Pre-ECC Correction Subheader: Channel Number (Byte 21) Data Register
(SHEAD05)
The pre-ECC correction subheader: channel number (byte 21) data register (SHEAD05) indicates
the channel number value in the subheader before ECC correction (byte 21).
Bit: 7
6
5
4
3
2
1
0
SHEAD05[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit Bit Name
Initial
Value R/W Description
7 to 0 SHEAD05[7:0] All 0 R
Indicate channel number value in the subheader
before ECC correction (byte 21).
For sectors not in Mode 2, this register contains the
byte of data at the corresponding position.
21.3.27 Pre-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD06)
The pre-ECC correction subheader: sub-mode (byte 22) data register (SHEAD06) indicates the
sub-mode value in the subheader before ECC correction (byte 22).
Bit: 7
6
5
4
3
2
1
0
SHEAD06[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit Bit Name
Initial
Value R/W Description
7 to 0 SHEAD06[7:0] All 0 R
Sub-Mode Value in Subheader Before ECC Correction
(Byte 22)
For sectors not in Mode 2, this register contains the
byte of data at the corresponding position.
Rev. 2.00 Mar. 14, 2008 Page 1112 of 1824
REJ09B0290-0200