SH7263 Datasheet, PDF (1025/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
mode
requested setting
Time Slave TXPR[30] = 0
&
MBC[30]!= 3'b000
&
CMAX!= 3'b111
&
MBC[31] = 3'b011
(Potential) TXPR[30] = 1
Time Master &
MBC[30] = 3'b000
&
DLC[30] > 0
&
CMAX!= 3'b111
&
MBC[31] = 3'b011
function
TCNTR is sampled at each SOF detected on the CAN Bus
and stored into an internal register. When a valid Time
Reference Message is received into Mailbox-31 the value of
TCNTR (stored at the SOF) is copied into Ref_Mark.
CCR embedded in the received Reference Message is
copied to CCR.
If Next_is_Gap = 1, IRR13 is set.
Two cases are covered:
(1) When a valid Time Reference message is received into
Mailbox-31 the value of TCNTR stored into an internal
register at the SOF is copied into Ref_Mark.
CCR embedded in the received Reference Message is
copied to CCR.
If Next_is_Gap = 1, IRR13 is set.
(2) When a Time Reference message is transmitted from
Mailbox-30 the value of TCNTR stored into an internal
register at the SOF is copied into Ref_Mark.
CCR is incremented when TTT of Mailbox-30 matches
with CYCTR .
CCR is embedded into the first data byte of the time
reference message
{ Data0[7:6], CCR[5:0] } .
• Setting Tx-Trigger Time
The Tx-Trigger Time(TTT) must be set in ascending order shown below, and the difference
between them has to satisfy the following expressions. TEW in the following expressions is the
register value.
TTT (Mailbox-24) < TTT (Mailbox-25) < TTT (Mailbox-26) < TTT (Mailbox-27) < TTT
(Mailbox-28) < TTT (Mailbox-29) < TTT (Mailbox-30)
and
TTT (Mailbox-i) – TTT (Mailbox- i-1) > TEW + the maximum frame length + 9
TTT (Mailbox-24) to TTT (Mailbox-29) correspond to Time_Marks, and TTT (Mailbox-30)
corresponds to Time_Ref showing the length of a basic cycle, respectively when working as
potential time master.
Rev. 2.00 Mar. 14, 2008 Page 991 of 1824
REJ09B0290-0200