SH7263 Datasheet, PDF (466/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Address
Mode Transfer Category
Request Bus Transfer
Usable
Mode Mode Size (Bits) Channels
Dual
On-chip peripheral module and on-chip All*¹
peripheral module
B/C*⁵ 8/16/32/128*² 0 to 7*³
On-chip memory and on-chip memory All*⁴
B/C 8/16/32/128 0 to 7*³
On-chip memory and memory-mapped All*⁴
external device
B/C 8/16/32/128 0 to 7*³
On-chip memory and on-chip peripheral All*¹
module
B/C*⁵ 8/16/32/128*² 0 to 7*³
On-chip memory and external memory All*⁴
B/C 8/16/32/128 0 to 7*³
Single
External device with DACK and external External B/C 8/16/32/128 0 to 3
memory
External device with DACK and memory- External B/C 8/16/32/128 0 to 3
mapped external device
[Legend]
B:
Burst
C: Cycle steal
Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all
available. However, in the case of internal module request, along with the exception of
MTU2 and CMT as the transfer request source, the requesting module must be
designated as the transfer source or the transfer destination.
2. Access size permitted for the on-chip peripheral module register functioning as the
transfer source or transfer destination.
3. If the transfer request is an external request, channels 0 to 3 are only available.
4. External requests, auto requests, and on-chip peripheral module requests are all
available. In the case of on-chip peripheral module requests, however, the CMT and
MTU2 are only available.
5. In the case of on-chip peripheral module request, only cycle steal except for the USB,
SSI, ROM-DEC, SRC, MTU2 and CMT as the transfer request source.
Rev. 2.00 Mar. 14, 2008 Page 432 of 1824
REJ09B0290-0200