SH7263 Datasheet, PDF (878/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
17.4 Operation
The I²C bus interface 3 can communicate either in I²C bus mode or clocked synchronous serial
mode by setting FS in SAR.
17.4.1 I²C Bus Format
Figure 17.3 shows the I²C bus formats. Figure 17.4 shows the I²C bus timing. The first frame
following a start condition always consists of eight bits.
(a) I²C bus format (FS = 0)
S
SLA
R/W A
1
7
11
1
DATA
n
A
1
m
A/A P
11
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m ≥ 1)
(b) I²C bus format (Start condition retransmission, FS = 0)
S
SLA
R/W A
DATA
A/A S
1
7
11
n1
11
1
m1
SLA
R/W A
7
11
1
DATA
n2
m2
A/A P
11
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
Figure 17.3 I²C Bus Formats
SDA
SCL
S
1-7
8
9
SLA
R/W A
1-7
8
9
DATA
A
1-7
8
9
DATA
A
P
Figure 17.4 I²C Bus Timing
[Legend]
S:
Start condition. The master device drives SDA from high to low while SCL is high.
SLA:
R/W:
Slave address
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge. The receive device drives SDA to low.
DATA: Transfer data
P:
Stop condition. The master device drives SDA from low to high while SCL is high.
Rev. 2.00 Mar. 14, 2008 Page 844 of 1824
REJ09B0290-0200