SH7263 Datasheet, PDF (1099/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
20.4.2 Reception Format
Figure 20.7 shows the relationship between the transfer format and each register during the IEBus
data reception.
[In slave reception]
Communications frame Master address
Slave address
Control bits
Message length bits
Data bits
Register
IEMA1, IEMA2
(*)
IEAR1, IEAR2
IERCTL
IERBFL
Note: * Received slave address is compared with IEAR1 and IEAR2. If they match,
the subsequent operations are performed.
IERB001 to IERB128
[In master reception]
Communications frame ^{Master address}
Slave address
Control bits
Message length bits
Data bits
Register
IEAR1, IEAR2
IESA1, IESA2
IEMCR
IERBFL
Figure 20.7 Relationship between Transfer Format
and Each Register during IEBus Data Reception
IERB001 to IERB128
Rev. 2.00 Mar. 14, 2008 Page 1065 of 1824
REJ09B0290-0200