SH7263 Datasheet, PDF (1586/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
Table 32.1 shows the transition conditions for entering the modes from the program execution
state, as well as the CPU and peripheral module states in each mode and the procedures for
canceling each mode.
Table 32.1 States of Power-Down Modes
Power-
Down
Mode
Sleep
mode
Transition
Conditions CPG
CPU
Execute
Running Halted
SLEEP
instruction
with STBY bit
in STBCR
cleared to 0
State*¹
On-Chip
RAM
(High- On-Chip
Speed) RAM
On-Chip
CPU
Cash (for Data Peripheral
Register Memory Retention) Modules RTC
Power External Canceling
supply Memory Procedure
Held
Running Running Running Running*² Running Auto-
• Interrupt
refresh
• Manual reset
• Power-on
reset
Software Execute
Halted
standby SLEEP
mode instruction
with STBY bit
in STBCR set
to 1 and
DEEP bit to 0
Halted
Held
Halted Halted
Halted
(contents ^(contents
are
are held*⁵)
held*⁵*⁶)
Deep
standby
mode
Execute
Halted
SLEEP
instruction
with STBY
and DEEP
bits in STBCR
set to 1
Halted
Halted
Halted Halted
Halted
(contents (contents
are not are held*³)
held)
• DMA address
error
Running*² Running Self-
• NMI interrupt
refresh
• IRQ interrupt
• Manual reset
• Power-on
reset
Running*² Halted Self-
• NMI interrupt*⁴
refresh
• IRQ interrupt*⁴
• Manual reset*⁴
• Power-on
reset*⁴
Rev. 2.00 Mar. 14, 2008 Page 1552 of 1824
REJ09B0290-0200