SH7263 Datasheet, PDF (433/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Bit
17
16
15,14
Bit Name
AM
AL
DM[1:0]
Initial
Value R/W Description
0
R/W Acknowledge Mode
Specifies whether DACK and TEND are output in data
read cycle or in data write cycle in dual address mode.
In single address mode, DACK and TEND are always
output regardless of the specification by this bit.
This bit is valid only in CHCR_0 to CHCR_3. This bit is
reserved in CHCR_4 to CHCR_7; it is always read as
0 and the write value should always be 0.
0: DACK and TEND output in read cycle (dual address
mode)
1: DACK and TEND output in write cycle (dual address
mode)
0
R/W Acknowledge Level
Specifies the DACK (acknowledge) signal output is
high active or low active.
This bit is valid only in CHCR_0 to CHCR_3. This bit is
reserved in CHCR_4 to CHCR_7; it is always read as
0 and the write value should always be 0.
0: Low-active output from DACK
1: High-active output from DACK
00
R/W Destination Address Mode
These bits select whether the DMA destination
address is incremented, decremented, or left fixed. (In
single address mode, DM1 and DM0 bits are ignored
when data is transferred to an external device with
DACK.)
00: Fixed destination address
01: Destination address is incremented (+1 in 8-bit
transfer, +2 in 16-bit transfer, +4 in 32-bit transfer,
+16 in 16-byte transfer)
10: Destination address is decremented (–1 in 8-bit
transfer, –2 in 16-bit transfer, –4 in 32-bit transfer,
setting prohibited in 16-byte transfer)
11: Setting prohibited
Rev. 2.00 Mar. 14, 2008 Page 399 of 1824
REJ09B0290-0200