SH7263 Datasheet, PDF (36/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Table 1.1 SH7263 Features
Items
CPU
Specification
• Renesas Technology original SuperH architecture
• Compatible with SH-1, SH-2, and SH-2E at object code level
• 32-bit internal data bus
• Support of an abundant register-set
⎯ Sixteen 32-bit general registers
⎯ Four 32-bit control registers
⎯ Four 32-bit system registers
⎯ Register bank for high-speed response to interrupts
• RISC-type instruction set (upward compatible with SH series)
⎯ Instruction length: 16-bit fixed-length basic instructions for improved
code efficiency and 32-bit instructions for high performance and
usability
⎯ Load/store architecture
⎯ Delayed branch instructions
⎯ Instruction set based on C language
• Superscalar architecture to execute two instructions at one time
including FPU
• Instruction execution time: Up to two instructions/cycle
• Address space: 4 Gbytes
• Internal multiplier
• Five-stage pipeline
• Harvard architecture
Rev. 2.00 Mar. 14, 2008 Page 2 of 1824
REJ09B0290-0200