SH7263 Datasheet, PDF (87/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Register indirect @(disp:4,
with
Rn)
displacement
The effective address is the sum of Rn and a 4-bit Byte:
displacement (disp). The value of disp is zero- Rn + disp
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
Word:
Rn + disp × 2
Longword:
Rn
Rn + disp × 4
disp
(zero-extended)
+
Rn + disp × 1/2/4
×
1/2/4
Register indirect @(disp:12, The effective address is the sum of Rn and a 12-
with
Rn)
bit
displacement
displacement (disp). The value of disp is zero-
extended.
Rn
+
Rn + disp
Byte:
Rn + disp
Word:
Rn + disp
Longword:
Rn + disp
disp
(zero-extended)
Indexed register @(R0,Rn) The effective address is the sum of Rn and R0.
indirect
Rn
Rn + R0
+
Rn + R0
GBR indirect
with
displacement
R0
@(disp:8,
GBR)
The effective address is the sum of GBR value Byte:
and an 8-bit displacement (disp). The value of GBR + disp
disp is zero-extended, and remains unchanged for _Word:
a byte operation, is doubled for a word operation, _{GBR + disp × 2}
and is quadrupled for a longword operation.
Longword:
GBR
GBR + disp × 4
disp
(zero-extended)
+
GBR
+ disp × 1/2/4
×
1/2/4
Rev. 2.00 Mar. 14, 2008 Page 53 of 1824
REJ09B0290-0200