SH7263 Datasheet, PDF (1420/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.3.13 LCDC Vertical Total Line Number Register (LDVTLNR)
LDVTLNR specifies the LCD panel's entire vertical size including the vertical retrace period.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
- VTLN10 VTLN9 VTLN8 VTLN7 VTLN6 VTLN5 VTLN4 VTLN3 VTLN2 VTLN1 VTLN0
Initial value: 0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 11 ⎯
10
VTLN10
9
VTLN9
8
VTLN8
7
VTLN7
6
VTLN6
5
VTLN5
4
VTLN4
3
VTLN3
2
VTLN2
1
VTLN1
0
VTLN0
Initial
Value R/W
All 0 R
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Vertical Total Line Number
Set the total number of vertical display lines (unit: line).
Specify to the value of (the number of total line) -1.
The minimum for the total number of vertical lines is 2
lines. The following conditions must be satisfied:
VTLN>=VDLN, VTLN>=1.
Example: For an 480-line LCD module and a vertical
period of 0 lines.
VTLN = (480+0) –1 = 479 = H'1DF
Rev. 2.00 Mar. 14, 2008 Page 1386 of 1824
REJ09B0290-0200