SH7263 Datasheet, PDF (1426/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.3.17 LCDC Power Management Mode Register (LDPMMR)
LDPMMR controls the power supply circuit that provides power to the LCD module. The usage
of two types of power-supply control pins, LCD_VCPWC and LCD_VEPWC, and turning on or
off the power supply function are selected.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ONC3 ONC2 ONC1 ONC0 OFFD3 OFFD2 OFFD1 OFFD0 - VCPE VEPE DONE -
-
LPS[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R
R
R
R
Initial
Bit
Bit Name Value R/W Description
15
ONC3
0
R/W LCDC Power-On Sequence Period
14
ONC2
0
R/W Set the period from LCD_VEPWC assertion to
13
ONC1
0
R/W ^{LCD_DON assertion in the power-on sequence of the}
LCD module in frame units.
12
ONC0
0
R/W
Specify to the value of (the period) -1.
This period is the (c) period in figures 26.4 to 26.7,
Power-Supply Control Sequence and States of the LCD
Module. For details on setting this register, see table
26.6, Available Power-Supply Control-Sequence
Periods at Typical Frame Rates. (The setting method is
common for ONA, ONB, OFFD, OFFE, and OFFF.)
11
OFFD3
0
R/W LCDC Power-Off Sequence Period
10
OFFD2
0
R/W Set the period from LCD_DON negation to
9
OFFD1
0
R/W ^{LCD_VEPWC negation in the power-off sequence of}
the LCD module in frame units.
8
OFFD0
0
R/W
Specify to the value of (the period) -1.
This period is the (d) period in figures 26.4 to 26.7,
Power-Supply Control Sequence and States of the LCD
Module.
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1392 of 1824
REJ09B0290-0200