SH7263 Datasheet, PDF (436/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
2
IE
0
R/W Interrupt Enable
Specifies whether or not an interrupt request is
generated to the CPU at the end of the DMA transfer.
Setting this bit to 1 generates an interrupt request
(DEI) to the CPU when TE bit is set to 1.
0: Disables an interrupt request
1: Enables an interrupt request
1
TE
0
R/(W)* Transfer End Flag
This bit is set to 1 when DMATCR becomes 0 and
DMA transfer ends.
The TE bit is not set to 1 in the following cases.
• DMA transfer ends due to an NMI interrupt or DMA
address error before DMATCR becomes 0.
• DMA transfer is ended by clearing the DE bit and
DME bit in DMA operation register (DMAOR).
To clear the TE bit, write 0 after reading TE = 1.
Even if the DE bit is set to 1 while the TEMASK bit is 0
and this bit is 1, transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
terminated
[Clearing condition]
• Writing 0 after reading TE = 1
1: DMA transfer ends by the specified count (DMATCR
= 0)
Rev. 2.00 Mar. 14, 2008 Page 402 of 1824
REJ09B0290-0200