SH7263 Datasheet, PDF (1786/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
Table 35.20 NAND Type Flash Memory Interface Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0 V, Ta = −40 to 85 °C
Item
Command output setup time
Command output hold time
Data output setup time
Data output hold time
Command to address transition
time 1
Command to address transition
time 2
FWE cycle time
FWE low pulse width
Symbol Min.
Max.
tNCDS
2 × tfcyc − 10 ⎯
tNCDH
1.5 × tfcyc − 5 ⎯
tNDOS
0.5 × twfcyc − 5 ⎯
tNDOH
0.5 × twfcyc − 10 ⎯
tNCDAD1
1.5 × tfcyc − 10 ⎯
Unit
ns
ns
ns
ns
ns
tNCDAD2
2 × tfcyc − 10
⎯
ns
tNWC
twfcyc − 5
⎯
ns
tNWP
0.5 × twfcyc − 5 ⎯
ns
FWE high pulse width
tNWH
0.5 × twfcyc − 5 ⎯
ns
Address to ready/busy transition time tNADRB ⎯
32 × tpcyc ns
Command to ready/busy transition
time
Ready/busy to data read transition
time 1
Ready/busy to data read transition
time 2
FSC cycle time
FSC low pulse width
tNCDRB
tNRBDR1
tNRBDR2
tNSCC
tNSP
⎯
10 × tpcyc ns
1.5 × tfcyc
⎯
ns
32 × tpcyc
⎯
ns
twfcyc − 5
⎯
ns
0.5 × twfcyc − 5 ⎯
ns
FSC high pulse width
Read data setup time
tNSPH
0.5 × twfcyc − 5 ⎯
ns
tNRDS
24
⎯
ns
Figure
Figures 35.69,
35.73
Figures 35.69,
35.70, 35.72,
35.73
Figures 35.69,
35.70
Figure 35.70
Figures 35.70,
35.72
Figures 35.69,
35.70, 35.72,
35.73
Figures 35.70,
35.72
Figures 35.70,
35.71
Figures 35.70,
35.71
Figure 35.71
Figures 35.71,
35.73
Figure 35.71
Figures 35.71,
35.73
Rev. 2.00 Mar. 14, 2008 Page 1752 of 1824
REJ09B0290-0200