SH7263 Datasheet, PDF (870/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
17.3.4 I²C Bus Interrupt Enable Register (ICIER)
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits
received.
Bit: 7
TIE
Initial value: 0
R/W: R/W
6
TEIE
0
R/W
5
4
3
RIE NAKIE STIE
0
0
0
R/W R/W R/W
2
1
0
ACKE ACKBR ACKBT
0
0
0
R/W R R/W
Initial
Bit
Bit Name Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1 or 0, this bit
enables or disables the transmit data empty interrupt
(TXI).
0: Transmit data empty interrupt request (TXI) is
disabled.
1: Transmit data empty interrupt request (TXI) is
enabled.
6
TEIE
0
R/W Transmit End Interrupt Enable
Enables or disables the transmit end interrupt (TEI) at
the rising of the ninth clock while the TDRE bit in ICSR
is 1. TEI can be canceled by clearing the TEND bit or
the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
5
RIE
0
R/W Receive Interrupt Enable
Enables or disables the receive data full interrupt
request (RXI) and the overrun error interrupt request
(ERI) in the clocked synchronous format when receive
data is transferred from ICDRS to ICDRR and the
RDRF bit in ICSR is set to 1. RXI can be canceled by
clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) are disabled.
1: Receive data full interrupt request (RXI) are enabled.
Rev. 2.00 Mar. 14, 2008 Page 836 of 1824
REJ09B0290-0200