SH7263 Datasheet, PDF (326/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Table 9.7 8-Bit External Device Access and Data Alignment in Big Endian
Data Bus
Operation
D31 to D23 to D15 to
D24 D16 D8 D7 to D0
Byte access at 0
⎯
⎯
⎯
Data
7 to 0
Byte access at 1
⎯
⎯
⎯
Data
7 to 0
Byte access at 2
⎯
⎯
⎯
Data
7 to 0
Byte access at 3
⎯
⎯
⎯
Data
7 to 0
Word
1st time ⎯
⎯
⎯
Data
access at 0 at 0
15 to 8
2nd time ⎯
⎯
⎯
Data
at 1
7 to 0
Word
1st time ⎯
⎯
⎯
Data
access at 2 at 2
15 to 8
2nd time ⎯
⎯
⎯
Data
at 3
7 to 0
Longword 1st time ⎯
⎯
⎯
Data
access at 0 at 0
31 to 24
2nd time ⎯
⎯
⎯
Data
at 1
23 to 16
3rd time ⎯
⎯
⎯
Data
at 2
15 to 8
4th time ⎯
⎯
⎯
Data
at 3
7 to 0
WE3,
DQMUU
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Strobe Signals
WE2,
DQMUL
WE1,
DQMLU
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
WE0,
DQMLL
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Rev. 2.00 Mar. 14, 2008 Page 292 of 1824
REJ09B0290-0200