SH7263 Datasheet, PDF (463/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.8 shows an example of DMA transfer timing in single address mode.
CK
A25 to A0
CSn
WEn
D31 to D0
DACKn
Address output to external memory space
Select signal to external memory space
Write strobe signal to external memory space
Data output from external device with DACK
DACK signal (active-low) to external device with DACK
(a) External device with DACK → External memory space (normal memory)
CK
A25 to A0
CSn
RD
Address output to external memory space
Select signal to external memory space
Read strobe signal to external memory space
D31 to D0
DACKn
Data output from external memory space
DACK signal (active-low) to external device with DACK
(b) External memory space (normal memory) → External device with DACK
Figure 10.8 Example of DMA Transfer Timing in Single Address Mode
(2) Bus Modes
There are two bus modes; cycle steal and burst. Select the mode by the TB bits in the channel
control registers (CHCR).
(a) Cycle Steal Mode
• Normal mode
In normal mode of cycle steal, the bus mastership is given to another bus master after a one-
transfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer
request occurs, the bus mastership is obtained from another bus master and a transfer is
performed for one transfer unit. When that transfer ends, the bus mastership is passed to
another bus master. This is repeated until the transfer end conditions are satisfied.
The cycle-steal normal mode can be used for any transfer section; transfer request source,
transfer source, and transfer destination.
Figure 10.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are;
Rev. 2.00 Mar. 14, 2008 Page 429 of 1824
REJ09B0290-0200