SH7263 Datasheet, PDF (1471/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
27.2.3 SRC Input Data Control Register (SRCIDCTRL)
SRCIDCTRL is a 16-bit readable/writable register that specifies the endian format of input data,
enables/disables the interrupt requests, and specifies the triggering number of data units.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
IED IEN
-
-
-
-
-
-
IFTRG[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R
R
R
R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 10 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9
IED
0
R/W Input Data Endian
Specifies the endian format of the input data.
0: Big endian
1: Little endian
8
IEN
0
R/W Input Data FIFO Empty Interrupt Enable
Enables/disables the input data FIFO empty interrupt
request to be issued when the number of data units in
the input FIFO becomes equal to or smaller than the
triggering number specified by the IFTRG1 and
IFTRG0 bits, thus resulting in the IINT bit in the SRC
status register (SRCSTAT) being set to 1.
0: Input data FIFO empty interrupt is disabled.
1: Input data FIFO empty interrupt is enabled.
7 to 2 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1437 of 1824
REJ09B0290-0200