SH7263 Datasheet, PDF (447/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Peripheral Module
SCIF_1
SCIF_2
SCIF_3
A/D converter_0
FLCTL_0
Setting Value for One
Channel ({MID, RID})
H'85
H'86
H'89
H'8A
H'8D
H'8E
H'B3
H'BB
FLCTL_1
H'BF
MID
B'100001
B'100010
B'100011
B'101100
B'101110
B'101111
RID
B'01
B'10
B'01
B'10
B'01
B'10
B'11
B'11
B'11
MTU2_0
MTU2_1
MTU2_2
MTU2_3
MTU2_4
CMT_0
CMT_1
H'E3
H'E7
H'EB
H'EF
H'F3
H'FB
H'FF
B'111000
B'11
B'111001
B'11
B'111010
B'11
B'111011
B'11
B'111100
B'11
B'111110
B'11
B'111111
B'11
Function
Transmit
Receive
Transmit
Receive
Transmit
Receive
⎯
Transmit/
receive data
Transmit/
receive
control code
⎯
⎯
⎯
⎯
⎯
⎯
⎯
When MID or RID other than the values listed in table 10.4 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to
RS0) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set, the
transfer request source is not accepted.
Rev. 2.00 Mar. 14, 2008 Page 413 of 1824
REJ09B0290-0200