SH7263 Datasheet, PDF (1148/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.30 Post-ECC Correction Header: Seconds Data Register (HEAD21)
The post-ECC correction header: seconds data register (HEAD21) indicates the seconds value in
the header after ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD21[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit
7 to 0
Bit Name
HEAD21[7:0]
Initial
Value
All 0
R/W Description
R
Seconds Value in Header After ECC Correction
When MSF_LBA_SEL = 1, this register indicates the
second byte of the total number of sectors calculated
from M, S, and F.
21.3.31 Post-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD22)
The post-ECC correction header: frames (1/75 second) data register (HEAD22) indicates the
frames value (1 frame = 1/75 seconds) in the header after ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD22[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit Bit Name
7 to 0 HEAD22[7:0]
Initial
Value R/W Description
All 0 R
Frames Value in Header After ECC Correction
When MSF_LBA_SEL = 1, this register indicates the
third byte of the total number of sectors calculated
from M, S, and F.
Rev. 2.00 Mar. 14, 2008 Page 1114 of 1824
REJ09B0290-0200