SH7263 Datasheet, PDF (1127/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.4 EDC/ECC Check Control Register (CROMCTL1)
The EDC/ECC check control register (CROMCTL1) controls EDC/ECC checking. The setting of
this register becomes valid at the sector-to-sector transition
Bit:
Initial value:
R/W:
7
M2F2
EDC
1
R/W
6
5
4
MD_DEC[2:0]
1
0
1
R/W R/W R/W
3
-
0
R/W
2
-
0
R/W
1
0
MD_PQREP[1:0]
0
1
R/W R/W
Initial
Bit Bit Name Value
7
M2F2EDC 1
6 to 4 MD_DEC 101
[2:0]
3, 2 ⎯
All 0
1, 0 MD_PQREP 01
[1:0]
R/W Description
R/W For Mode 2 Form 2, disables the EDC function for
sectors where all bits of the EDC are 0.
When this bit set to 1 and all bits of the EDC for a Mode
2 Form 2 sector are 0, an IERR interrupt is not
generated even if the result of EDC checking is ‘fail’.
R/W EDC/ECC Checking Mode Select
000: No checking
001: EDC only
010: Q correction + EDC
011: P correction + EDC
100: QP correction + EDC
101: PQ correction + EDC
110: Setting prohibited
111: Setting prohibited
R/W Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Number of Iterations of PQ or QP Correction
Number of correction iterations when PQ- or QP-
correction is specified by MD_DEC[2:0].
00: Setting prohibited
01: One iteration
10: Two iterations
11: Three iterations
Rev. 2.00 Mar. 14, 2008 Page 1093 of 1824
REJ09B0290-0200