SH7263 Datasheet, PDF (234/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
Bit
19
18
17, 16
15
14
Bit Name
UTOD1
UTOD0
CKS[1:0]
SCMFC0
SCMFC1
Initial
Value
0
0
00
0
0
R/W Description
R/W UBCTRG Output Disable 1
Specifies whether a trigger signal is output to the
UBCTRG pin when a break condition for channel 1 is
satisfied.
0: Outputs a trigger signal to the UBCTRG pin when a
break condition for channel 1 is satisfied
1: Does not output a trigger signal to the UBCTRG pin
when a break condition for channel 1 is satisfied
R/W UBCTRG Output Disable 0
Specifies whether a trigger signal is output to the
UBCTRG pin when a break condition for channel 0 is
satisfied.
0: Outputs a trigger signal to the UBCTRG pin when a
break condition for channel 0 is satisfied
1: Does not output a trigger signal to the UBCTRG pin
when a break condition for channel 0 is satisfied
R/W Clock Select
Specifies the pulse width output to the UBCTRG pin
when a break condition is satisfied.
00: Pulse width of UBCTRG is one bus clock cycle
01: Pulse width of UBCTRG is two bus clock cycles
10: Pulse width of UBCTRG is four bus clock cycles
11: Pulse width of UBCTRG is eight bus clock cycles
R/W C Bus Cycle Condition Match Flag 0
When the C bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 0 does not
match
1: The C bus cycle condition for channel 0 matches
R/W C Bus Cycle Condition Match Flag 1
When the C bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 1 does not
match
1: The C bus cycle condition for channel 1 matches
Rev. 2.00 Mar. 14, 2008 Page 200 of 1824
REJ09B0290-0200